So you will need to think about what signal needs to be of what type and what types of operands the functions you are using require and cast accordingly. An arithmetic shift fills the bits vacated at the left end on a right shift with copies of the sign bit, since for signed twos complement integers all bits to. The basic problem you are having is one of type conversions. OUTPUT A(N downto to_integer(unsigned(X))), others => A(N)) WHEN OPERATION = "1001" ELSE I think the proper casts would be something like this (but you'll have to double check me as I don't have a VHDL compiler on this machine): -Declaration So you can define your inputs and outputs as BIT_VECTOR instead of STD_LOGIC_VECTOR and then use a cast to get just your X into an integer. The left operand must be a BIT_VECTOR and the right must be an integer. If you want to use sra, then you need to use the correct types. There are a couple of ways to go with this. (A <= X(N) & X(N downto 1)) WHEN OPERATION = "1001" ELSE STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B)) WHEN OPERATION = "1000" ELSE STD_LOGIC_VECTOR(SIGNED(A) + SIGNED(B)) WHEN OPERATION = "0111" ELSE Hello, Im a new user of VHDL and I dont manage to shifting a stdlogicvector. STD_LOGIC_VECTOR(SIGNED(A) - 1) WHEN OPERATION = "0110" ELSE STD_LOGIC_VECTOR(SIGNED(A) + 1) WHEN OPERATION = "0101" ELSE TEMP_OUTPUT <= (A) WHEN OPERATION = "0000" ELSE Sll Shift left logical Srl Shift right logical Sla Shift left arithmetic Sra Shift right arithmetic Rol Rotate left Ror Rotate Right. Signal TEMP_OUTPUT : STD_LOGIC_VECTOR(N downto 0) OPERATION : in STD_LOGIC_VECTOR(3 downto 0) -Allows us up to 16 operationsĪLU_OUTPUT : out STD_LOGIC_VECTOR(N downto 0)) Uncomment the following library declaration if instantiating arithmetic functions with Signed or Unsigned values Uncomment the following library declaration if using Could anyone point me in the right direction? To reiterate, I need to shift left/right A by X bits. This causes Type of OUTPUT is incompatible with type of <= error
Or because it's within a WHEN statement: OUTPUT <= (A <= X(N) & X(N downto 1)) WHEN OPERATION = "1001" ELSE OUTPUT <= (A sra X) WHEN OPERATION = "0000" ELSE However the methods I know of shifting left/right, either won't work because the values are defined as STD_LOGIC_VECTOR: -DeclarationĪ, B, X : in STD_LOGIC_VECTOR(N downto 0) This website goes into great detail about the history of these VHDL shift operators and discusses why they have been replaced by shift_right() and shift_left() functions.I'm attempting to create a parametrizable ALU which handles N-Bit signed data. However these shift operators never worked correctly and were removed from the language. Unsigned=Logical, Signed=ArithmeticĪt one point, there were actual shift operators built into VHDL.
A shift register implements a FIFO of fixed length. You can dramatically reduce the number of consumed resources by choosing the right shift register implementation for your needs and FPGA architecture. Shift functions can perform both logical (zero-fill) and arithmetic (keep sign) shifts There are many ways to create a shift register in VHDL, though not all of them are equal.Shift functions are found in numeric_std package file.
Arithmetic shift means that the replaced bits are substituted in order to maintain the sign of the original number. A logical shift means that the new bits are replaced with zeros. There are two types of shifts: Logical and Arithmetic. Shifting is a quick way to create a Shift Register. Signal to shift, the second is the number of bits to shift.
The functions take two inputs: the first is the Performing shifts in VHDL is done via functions: shift_left() and Shift Left, Shift Right – VHDL Example Create shift registers in your FPGA or ASIC
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